At this time, the process statement proceeds through lines 12, 13, 14, and back to It is again suspended at line From the simulation waveform, it is easy to see that signal Q follows signal D with a delay. Whatever the value of signal D before the rising edge of the clock CLK, it is captured as the value of signal Q. This is the reason we often refer to a D flip-flop as a delay flip-flop. The D flip-flop has only one Q output; output Qn inverted Q is not connected.
A temporary signal DFF is declared in line 9, which is used in line Output signals Q and Qn are assigned in line The above D flip-flop is the simplest version. It does not have the synchronous or asynchronous reset input. Every target signal signals appearing on the left-hand side of the signal assignment state- ments affected by the rising edge expression infers a number of flip-flops depending on the target signal width.
Processes seqO lines 13 to 17 and seql lines 18 to 26 use a wait statement inside a process statement without a sensitivity list. The target signal to infer a flip- flop can have a Boolean expression on the right-hand side of the signal assignment statements as in lines 16, 24, and The target signal value can also be affected by other sequential statements such as the if statement in lines 21 to These Boolean expressions and sequential statements would result in combination circuits before the D input of the D flip-flop as shown in Figure synthesized schematic.
Processes seq2 lines 28 to 35 and seq3 lines 36 to 46 use a process statement with a sensi- 8 Chapter 2 VHDL and Digital Circuit Primitives tivity list. There is no wait statement inside the process statement.
As we recall, a process statement should have either a sensitivity list or at least a wait statement , but not both. SRSTn is used in lines 21, 26, 39, and 40 to show various ways to synchronously reset the flip-flops. The synchronous behavior is modeled by checking the rising edge before the SRSTn signal affects the target signal values.
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Lines 26, 39, and 40 to 44 are also using SRSTn to synchronously reset the flip-flops. If the reset check and the target signal are assigned before the rising edge clock check, the flip- flop will have asynchronous behavior; the change of the flip-flop output value does not wait until the rising edge of the clock. For example, in process seq2, line 30 checks whether the asynchronous reset signal and line 31 assigns DOUT 2 before the rising edge clock check in line Figure shows another synthesized schematic for the same ffs.
Note that the flip-flops with synchronous inputs are synthesized with cell name SFD2. The synchronous reset inputs of the flip-flops are either connected to the SRSTn directly or the output of a combination circuit gate.
The schematic in Figure does not use any synchronous reset flip-flops so that the synchronous behavior is done by combining the SRSTn signal with combinational gates to feed the D inputs of the flip-flops. The cells being used in Figure are listed below. The area of each cell is shown in the rightmost column.
The unit of the area is commonly referred to as the gate count. Note that FD1 flip-flop has a gate count of seven. The total gate count is You are encouraged to develop a feeling and sense of close estimate of the gate count for any design, even before it is designed. They function exactly the same except for their speed differences. Their total gate counts are also different. As we have stated above, it is a common practice to use synthesis tools to try to meet the speed requirements with the lowest possible gate count by using synthesis constraints.
The synthesis constraints will be illustrated throughout later chapters. Figure shows the synthesized schematic. The JK flip-flop has a gate count of nine. The function of a JK flip-flop can also be implemented with a D flip-flop. Fig- ure shows an example. It has a total gate count of You can see that the same functionality same VHDL code can be synthesized with different schematics. This is achieved by synthesis commands to use only the D flip-flops. Figure Synthesized schematic for jkff. The synchronous and asynchronous reset for a JK flip-flop is similar to the D flip-flop.
It is also common to have synchronous and asynchronous preset D and JK flip-flops. What do we do when a flip-flop has both asynchronous preset and reset clear? The following VHDL code can be used. Note that if statements always infer a priority of execution.
Figure shows the synthesized sche- matic. This is not the same as the priority of the cell FD3. When the latch enable input LE is asserted, Q gets the same value as D. When LE is deas- serted, Q retains its old value. Lines 4 to 11 specify the VHDL entity. The behavior of a latch can be described in a VHDL process statement as shown in lines 14 to The if statement does not have the else clause.
A latch is inferred when- ever a target signal is not assigned a value its old value is retained in an execution path of a conditional statement such as the if and case statement. On the other hand, in process seq3, the RSTn is checked in line 40, which is inside the if statement starting in line The latch is syn- chronously reset. The sequential statements inside the process statements as shown in process seqO, seql, seq2, and seq3 to describe latches can be written as a VHDL procedure.
Digital Design and Modeling with VHDL and Synthesis
The package named pack is referenced in line 3. The following summarizes the cells used in the schematic. Note that a latch has a gate count of five. When EN is asserted, Y gets the same value as D. The following VHDL code shows various ways that three-state buffers can be inferred.
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Lines 4 to 9 declare the VHDL entity. The package pack is referenced in line 3. The following list summarizes the cell area. Note that a three-state buffer has a gate count of four. The following VHDL code shows a simple example. This kind of connection is commonly used in an internal three-state bus and a bidirectional three-state bus which will be further discussed. The simulation of this example is left as Exercise 2.
These basic gates can be generated with various VHDL constructs. Lines 11 and 12 use the conditional signal assignment statement to generate Y2 and Y3. Lines 13 to 20 use a process statement with an if statement to generate Y4. The key is to write efficient good VHDL to model the circuit function correctly.
Most of the rest are left to the synthesis tools to generate function- ally correct circuits that satisfy design requirements. Line 14 describes a multiplexer function. A multiplexer is also called a selector because the output is selected from the inputs based on the selection signal. In line 14, D4 is the selection signal. Line 24 is a concurrent procedure call statement. Lines 15 to 22 use a pro- cess statement with an if statement inside. Note that the sensitivity list line 15 should include all signals that are read within the process statement.
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Figure schematic has the following area statistic. Based on these two sche- matics and area statistics, they have a different number of gates, interconnect nets, and total area measurements. Their timing delays are not shown here, but they are also dif- ferent. However, they should have the same logical function. They conform to the golden rule of synthesis: meet the timing requirement speed with the smallest possi- ble area.
When the design is big and complex, there is no time to worry about what types of combination gates synthesis tools use for the design. The particular type of combinational gates used by the synthesis tools should be the lower priority that designers need to worry. Designers can spend more time on the architecture, function- ality, speed, and area requirements by applying the synthesis tools to achieve their goals.